PXD10RM Datasheet, PDF (1041/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

30.4.3.21 SFM Interrupt and DMA Request Select and Enable Register
(QSPI_SFMRSER)
The QSPI_SFMRSER register provides enables and selectors for all interrupts in serial flash mode.
Address: QSPI_BASE + 0x164
Write: Anytime
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0
0000
000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0
0
0000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-21. SFM Interrupt and DMA Request Select and Enable Register (QSPI_SFMRSER)
Table 30-34. QSPI_SFMRSER Field Descriptions
Field
TBFIE
TBUIE
RBDDE
RBOIE
RBDIE
ABOIE
IPAEIE
IPIEIE
ICEIE
TFIE
Description
TX Buffer Fill Interrupt Enable
TX Buffer Underrun Interrupt Enable
RX Buffer Drain DMA Enable: Enables generation of DMA requests for RX Buffer Drain. When
this bit is set DMA requests via the ipd_req_rfdf line are generated as long as the
QSPI_SFMSR[RXNE] status bit is set.
0 No DMA request will be generated
1 DMA request will be generated
RX Buffer Overflow Interrupt Enable
RX Buffer Drain Interrupt Enable: Enables generation of IRQ requests for RX Buffer Drain. When
this bit is set the ipi_int_rfdf line is asserted as long as the QSPI_SFMSR[RBDF] flag is set.
0 No RBDF interrupt will be generated
1 RBDF Interrupt will be generated
AHB Buffer Overflow Interrupt Enable
IP Command Trigger during AHB Access Error Interrupt Enable
IP Command Trigger during IP Access Error Interrupt Enable
Instruction Code Error Interrupt Enable
Transaction Finished Interrupt Enable
30.4.4 AHB Bus Register Memory Map Descriptions
This chapter contains definitions of registers in the AMBA address space.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-37