PXD10RM Datasheet, PDF (323/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

In Figure 11-20, time ‘A’ shows the one clock interval. Time ‘B’ is user programmable from a minimum
of two system clocks.
System clock
CS
Frame 0
Frame 1
SCK
CPOL = 0
AB
CPOL = 1
Figure 11-20. Polarity Switching between Frames
11.8.6 Continuous Serial Communications Clock
The DSPI provides the option of generating a continuous SCK signal for slave peripherals that require a
continuous clock.
Continuous SCK is enabled by setting the CONT_SCKE bit in the DSPIx_MCR. Continuous SCK is valid
in all configurations.
Continuous SCK is only supported for CPHA = 1. Setting CPHA = 0 is ignored if the CONT_SCKE bit is
set. Continuous SCK is supported for modified transfer format.
Clock and transfer attributes for the continuous SCK mode are set according to the following rules:
• When the DSPI is in SPI configuration, CTAR0 is used initially. At the start of each SPI frame
transfer, the CTAR specified by the CTAS for the frame is used.
• In all configurations, the currently selected CTAR remains in use until the start of a frame with a
different CTAR specified, or the continuous SCK mode is terminated.
The device is designed to use the same baud rate for all transfers made while using the continuous SCK.
Switching clock polarity between frames while using continuous SCK can cause errors in the transfer.
Continuous SCK operation is not guaranteed if the DSPI is put into module disable mode.
Enabling continuous SCK disables the CS to SCK delay and the After SCK delay. The delay after transfer
is fixed at one SCK cycle. Figure 11-21 shows timing diagram for continuous SCK format with continuous
selection disabled.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-41