PXD10RM Datasheet, PDF (641/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

17.4.1.3 Modes of Operation
The PFLASH2P_LCA module does not support any special modes of operation. Its operation is driven
from the AMBA-AHB memory references it receives from the platform’s bus masters. Its configuration is
defined by the setting of its programming model registers, physically located as part of the flash array
modules.
17.4.2 External Signal Descriptions
The PFLASH2P_LCA does not directly interface with any external signals. As shown in Figure 17-42 and
Figure 17-43, its primary internal interfaces include two input connections from AMBA-AHB crossbar (or
memory protection unit) slave ports and output connections with up to three banks (2 code and 1 data) of
flash memory, each containing one or more instantiations of the low-cost flash array. Additionally, the
operating configuration for the PFLASH2P_LCA is defined by the contents of certain bank0 array0
registers which are inputs to the module.
A summary of the major PFLASH2p_LCA internal connections is shown in Table 17-61.
Table 17-61. PFLASH2P_LCA Module Connections
PFLASH2P_LCA
Connection
Description
Input p0
Input p1
Output b0
Output b1
Output b2
Processor Core
Non-core Masters
Bank0, Code Flash
Bank1, Data Flash
Bank2, Code Flash
17.4.3 Memory Map and Register Definition
There are two memory maps associated with the PFLASH2P_LCA: one for the flash memory space and
another for the program-visible control and configuration registers. The flash memory space is accessed
via the AMBA-AHB ports while the program-visible registers are accessed via the slave peripheral bus.
Details on both memory spaces are provided in Section 17.4.3.1, Memory Map”.
There are no program-visible registers that physically reside inside the PFLASH2P_LCA. Rather, the
PFLASH2P_LCA receives control and configuration information from the flash array controller(s) to
determine the operating configuration. These are part of the flash array’s configuration registers mapped
into its slave peripheral (IPS) address space but are described here.
17.4.3.1 Memory Map
First, consider the flash memory space accessed via transactions from the PFLASH2P_LCA’s AHB ports.
To support the three separate flash memory banks, the PFLASH2P_LCA controller uses address bits 23
and 19 (haddr[23, 19]) to steer the access to the appropriate memory bank. The address decode allocates
two 4 Mbyte spaces for bank0 and bank2 and an 8 Mbyte space for bank1. In addition to the actual flash
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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