PXD10RM Datasheet, PDF (987/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Offset channel_base + 0x0C
Access: Read/Write
0
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R0
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W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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R0
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0 TIF
W
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
TIF
Figure 27-6. Timer Flag Register (TFLG)
Table 27-7. TFLG Field Descriptions
Description
Time Interrupt Flag. TIF is set to 1 at the end of the timer period.This flag can be cleared only by
writing it with a 1. Writing a 0 has no effect. If enabled (TIE = 1), TIF causes an interrupt request.
0 Time-out has not yet occurred
1 Time-out has occurred
27.4 Functional Description
27.4.1 General
This section gives detailed information on the internal operation of the module. Each timer can be used to
generate trigger pulses as well as to generate interrupts, each interrupt will be available on a separate
interrupt line.
27.4.1.1 Timers
The timers generate triggers at periodic intervals, when enabled. They load their start values, as specified
in their LDVAL registers, then count down until they reach 0. Then they load their respective start value
again. Each time a timer reaches 0, it will generate a trigger pulse, and set the interrupt flag.
All interrupts can be enabled or masked (by setting the TIE bits in the TCTRL registers). A new interrupt
can be generated only after the previous one is cleared.
If desired, the current counter value of the timer can be read via the CVAL registers.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
27-7