PXD10RM Datasheet, PDF (728/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

19.9.3 e200z0 OnCE Controller Register Description
Most e200z0 OnCE debug registers are fully documented in the e200z0 Reference Manual.
19.9.3.1 OnCE Command Register (OCMD)
The OnCE command register (OCMD) is a 10-bit shift register that receives its serial data from the TDI
pin and serves as the instruction register (IR). It holds the 10-bit commands to be used as input for the
e200z0 OnCE Decoder. The OCMD is shown in Table 19-5. The OCMD is updated when the TAP
controller enters the update-IR state. It contains fields for controlling access to a resource, as well as
controlling single-step operation and exit from OnCE mode.
Although the OCMD is updated during the update-IR TAP controller state, the corresponding resource is
accessed in the DR scan sequence of the TAP controller, and as such, the update-DR state must be
transitioned through in order for an access to occur. In addition, the update-DR state must also be
transitioned through in order for the single-step and/or exit functionality to be performed, even though the
command appears to have no data resource requirement associated with it.
0
1
2
3
R
R/W GO EX
W
4
5
6
7
8
9
RS[0:6]
Reset: 0
0
0
0
0
1
1
0
1
1
Table 19-5. OnCE Command Register (OCMD)
Table 19-6. e200z0 OnCE Register Addressing
RS[0:6]
000 0000 – 000 0001
000 0010
000 0011 – 000 1111
001 0000
001 0001
001 0010
001 0011 – 001 1111
010 0000
010 0001
010 0010
010 0011
010 0100
010 0101
010 0110
Register Selected
Reserved
JTAG ID (read-only)
Reserved
CPU Scan Register (CPUSCR)
No Register Selected (Bypass)
OnCE Control Register (OCR)
Reserved
Instruction Address Compare 1 (IAC1)
Instruction Address Compare 2 (IAC2)
Instruction Address Compare 3 (IAC3)
Instruction Address Compare 4 (IAC4)
Data Address Compare 1 (DAC1)
Data Address Compare 2 (DAC2)
Data Value Compare 1 (DVC1)
19-12
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor