PXD10RM Datasheet, PDF (457/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

NOTE
Because of the dynamic nature of the system (i.e. DMA channel priorities,
bus arbitration, interrupt service routine lengths, etc.), the number of clock
cycles between a trigger and the actual DMA transfer cannot be guaranteed.
Source #1
Source #2
Source #3
Trigger #0
Trigger #1
DMA Channel #0
Source #63
Always #1
Trigger #3
DMA Channel #3
Always #4
Figure 13-3. DMA Mux triggered channels
The DMA channel triggering capability allows the system to “schedule” regular DMA transfers, usually
on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by
gating the request from the Peripheral to the DMA until a trigger event has been seen. This is illustrated
in Figure 13-4.
Periph Request
Trigger
DMA Request
Figure 13-4. DMA Mux Channel Triggering: Normal Operation
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
13-7