PXD10RM Datasheet, PDF (1123/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Similarly, the 4 bits configured by the software comprise the signal ch2_sel[0:3], thus leading to selection
of output from the second PWM channel being used for sound genereation. This output from second
channel will be the one having fixed duty cycle and variable frequency.
Simultaneously, mono/poly_b is configured such that for monotonic sound generation its value will be
one, and hence the output from the and gate will be selected i.e. the ANDing of signals from MuxA
(variable duty cycle, fixed frequency) and MuxB (fixed duty cycle, variable frequency) will produce
monotonic sound.
In case where polyphonic sound is to be generated, the software configures the MODE_SEL register
through the IPS interface such that the set of 4 bits (CH1_SEL[0:3]) can be used to select output from the
PWM channel being used for sound generation.
Simultaneously, mono/poly_b is configured such that for polyphonic sound generation its value will be
zero, and hence the output corresponding to the signal producing polyphonic sound will be selected.
The suggested sequence of events for sound generation controlled by SOUND_CTRL[0:2] is:
1. Initially SOUND_CTRL[0:2] is 3’b000.
2. Program the SOUND_DURATION/ HIGH_PERIOD/LOW_PERIOD registers’ values,
depending on the mode of sound generation which is desired.
3. Program the SOUND_CTRL[0:2] bits to the new value depending on the mode desired.
4. Edge detector detects the change on SOUND_CTRL[0:2] bits.
5. On the next clock edge after the edge detection, the sound generation starts.
6. In cases where the sound duration depends on the value in SOUND_DURATION register, the
sound generation stops when SOUND_DURATION counter reaches zero. An interrupt is raised as
soon as the SOUND_DURATION counter reaches zero. In these cases, the ISR changes the
SOUND_CTRL[0:2] to 3’b000 from the present value.
In other cases, where SOUND_DURATION counter has no role to play, the sound generation stops when
the SOUND_CTRL[0:2] bits are changed asynchronously by the software.
33.4.1 Interrupts
SGL generates the interrupt signal ipi_int_sgl. The generation of this interrupt is enabled if the
MODE_SEL[SDCIE] bit is ‘1’. If this bit is ‘0’, then the interrupt is disabled.
The interrupt is generated whenever the SOUND_DURATION counter reaches ‘0’ in cases where sound
is being generated for a predetermined duration of time (ie . SOUND_DURATION register value is
controlling sound duration).
The SGL_STATUS[SDCIF] bit indicates the generation of interrupt. It is set whenever an interrupt is
generated irrespective of the value of the SDCIE bit. It can be cleared by writing ‘1’ to it.
The interrupt signal ipi_int_sgl is asserted if the SDCIF flag is set and the SDCIE bit is set.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
33-9