PXD10RM Datasheet, PDF (575/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 17-18. ADR field descriptions (continued)
Field
Description
9:28 AD22-3: ADdress 22-3 (Read Only)
The Address Register provides the first failing address in the event of ECC error (MCR.EER set) or the
first failing address in the event of RWW error (MCR.RWE set), or the address of a failure that may have
occurred in a FPEC operation (MCR.PEG cleared). The Address Register provides also the first address
at which a ECC single error correction occurs (MCR.EDC set), if the SoC is configured to show this
feature.
The ECC double error detection takes the highest priority, followed by the RWW error, the FPEC error and
the ECC single error correction. When accessed ADR will provide the address related to the first event
occurred with the highest priority. The priorities between these 4 possible events is summarized in the
following table.
This address is always a Double Word address that selects 64 bits.
In case of a simultaneous ECC Double Error Detection on both Double Words of the same page, bit AD3
will output 0. The same is valid for a simultaneous ECC Single Error Correction on both Double Words of
the same page.
In User Mode the Address Register is read only.
29:31 Reserved (Read Only).
Write these bits has no effect and read these bits always outputs 0.
Priority Level
1
2
3
4
Table 17-19. ADR content: priority list
Error Flag
MCR.EER = 1
MCR.RWE = 1
MCR.PEG = 0
MCR.EDC = 1
ADR content
Address of first ECC Double Error
Address of first RWW Error
Address of first FPEC Error
Address of first ECC Single Error Correction
17.2.6.11 Bus Interface Unit 0 register (BIU0)
Address Offset: 0x0001C
Reset value: 0xXXXXXXXX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BI031 BI030 BI029 BI028 BI027 BI026 BI025 BI024 BI023 BI022 BI021 BI020 BI019 BI018 BI017 BI016
rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
BI015 BI014 BI013 BI012 BI011 BI010 BI009 BI008 BI007 BI006 BI005 BI004 BI003 BI002 BI001 BI000
rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X
Figure 17-10. Bus Interface Unit 0 register (BIU0)
The Bus Interface Unit 0 Register provides a mean for BIU specific information, or BIU configuration
information to be stored. Please see Section 17.4.3.2.1, Platform Flash Configuration Register 0
(PFCR0),” for more information about register description.
This register is present only in Code Flash 0.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
17-25