PXD10RM Datasheet, PDF (245/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

address: UC[n] base address + 0x0C
0
1
2
3
4
5
6
7
8
R
UCPR
0
FREN ODIS ODISSL[0:1] UCPRE[0:1]
DMA
W
EN
RESET: ₀
0
0
0
0
0
0
0
0
9
10 11 12 13 14 15
IF[0:3]
0
FCK FEN
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R₀
W
0
0
0
0
FORC FORC
MA MB
BSL[0:1]
EDSE EDPO
L
L
MODE[0:6]
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or reserved
Figure 9-15. eMIOS200 UC Control Register (EMIOSC[n])
Table 9-14. EMIOSC[n] Field Descriptions
Field
Description
bit 0
FREN
Freeze Enable bit
The FREN bit, if set and validated by FRZ bit in EMIOSMCR register allows the channel to enter
freeze state, freezing all registers values when in debug mode and allowing the MCU to perform
debug functions.
1 = Freeze UC registers values
0 = Normal operation
bit 1
ODIS
Output Disable bit
The ODIS bit allows disabling the output pin when running any of the output modes with the exception
of GPIO mode.
1 = If the selected Output Disable Input signal is asserted, the output pin goes to EDPOL for
OPWFMB and OPWMB modes and to the complement of EDPOL for other output modes, but the
Unified Channel continues to operate normally, i.e., it continues to produce FLAG and matches.
When the selected Output Disable Input signal is negated, the output pin operates normally
0 = The output pin operates normally
bit 2:3 Output Disable select bits
ODISSL[0:1] The ODISSL[0:1] bits select one of the four output disable input signals, as shown in Table 9-15.
bit 4:5 Prescaler bits
UCPRE[0:1] The UCPRE[0:1] bits select the clock divider value for the internal prescaler of Unified Channel, as
shown in Table 9-16.
bit 6
UCPREN
Prescaler Enable bit
The UCPREN bit enables the prescaler counter.
1 = Prescaler enabled
0 = Prescaler disabled (no clock)0:1
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-19