PXD10RM Datasheet, PDF (414/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

The three 16-bit formats (RGB565, ARGB1555, and ARGB4444) are promoted to full 8 bit per
component format by shifting the bits left so that the MSB of the component in the 16-bit format becomes
the MSB of the 24/32 bpp (bit per pixel) format, and the LSB is filled with the value of the MSB. For
example, an RGB565 value of 10000:010000:11111 becomes 10000111:0100000000:11111111.
There are four indexed color formats where the data in the graphic does not define the RGB color to
display. Instead, the data defines the entry in a color look-up table (CLUT) that contains a palette of RGB
colors. The maximum number of colors in the CLUT is defined by the size of the data stored in the graphic.
For 1 bpp graphics, there is a maximum of two colors in the CLUT. For 2 bpp, there is a maximum of four
colors. For 4 bpp and 8 bpp data, the maximums are 16 and 256 colors, respectively. The address of the
first value in the CLUT is defined in the LUOFFS bit field of register 4 and the CLUT is the RAM block
dedicated to the DCU which is described in Section 12.4.7, CLUT/Tile RAM”. Since the RGB values
stored in the CLUT are 24-bit RGB, there is no need for further adjustment before blending.
There are four additional formats defined by the BPP bit field. These configure the graphic in transparency
mode and luminance mode (see Section 12.4.5.6, Transparency mode and blending” and Section 12.4.5.7,
Luminance mode” respectively).
There is a set storage format for each data format provided by the DCU. These formats can be seen in
Table 12-54 to Table 12-60.
For 32 bpp format, data expected in the memory is in the form ARGB8888.
Table 12-54. Data layout for 32 bpp
Address offset
0x00
0x04
0x08
[7:0]
B0
B1
B2
[15:8]
G0
G1
G2
[23:16]
R0
R1
R2
[31:24]
A0
A1
A2
For 24 bpp format, data expected in the memory is in the form RGB888.
Table 12-55. Data Layout for 24 bpp
Address offset
0x00
0x04
0x08
[7:0]
B0
G1
R2
[15:8]
G0
R1
B3
[23:16]
R0
B2
G3
[31:24]
B1
G2
R3
For 16 bpp, data expected is in the form of RGB565, ARGB1555 or ARGB4444.
Table 12-56. Data Layout for 16 bpp
Address offset
0x00
0x04
0x08
[7:0]
pixel0[15:8]
pixel2[15:8]
pixel4[15:8]
[15:8]
pixel0[7:0]
pixel2[7:0]
pixel4[7:0]
[23:16]
pixel1[15:8]
pixel3[15:8]
pixel5[15:8]
[31:24]
pixel1[7:0]
pixel3[7:0]
pixel5[7:0]
12-82
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor