PXD10RM Datasheet, PDF (534/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

• RAM ECC Master Number Register (REMR)
• RAM ECC Attributes Register (REAT)
• RAM ECC Data Register (REDR)
The details on the ECC registers are provided in the subsequent sections. If the design does not include
ECC on the memories, these addresses are reserved locations within the ECSM’s programming model.
16.4.2.8 ECC Configuration Register (ECR)
The ECC Configuration Register is an 8-bit control register for specifying which types of memory errors
are reported. In all systems with ECC, the occurrence of a non-correctable error causes the current access
to be terminated with an error condition. In many cases, this error termination is reported directly by the
initiating bus master. However, there are certain situations where the occurrence of this type of
non-correctable error is not reported by the master. Examples include speculative instruction fetches which
are discarded due to a change-of-flow operation, and buffered operand writes. The ECC reporting logic in
the ECSM provides an optional error interrupt mechanism to signal all non-correctable memory errors. In
addition to the interrupt generation, the ECSM captures specific information (memory address, attributes
and data, bus master number, etc.) which may be useful for subsequent failure analysis.
The reporting of single-bit memory corrections can only be enabled via a an SoC-configurable module
input signal. While not directly accessible to a user, this capability is viewed as important for error logging
and failure analysis.
See Figure 16-7 and Table 16-8 for the ECC Configuration Register definition.
Register address: ECSM Base + 0x43
0
R
0
W
RESET:
0
1
2
3
4
0
0
ER1BR
EF1BR
0
0
0
0
5
6
7
0
ERNCR
EFNCR
0
0
0
= Unimplemented
Figure 16-7. ECC Configuration (ECR) Register
Table 16-8. ECC Configuration (ECR) Field Descriptions
Name
2
ER1BR
Description
Enable RAM 1-bit Reporting
0 = Reporting of single-bit RAM corrections is disabled.
1 = Reporting of single-bit RAM corrections is enabled.
This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a
single-bit RAM correction generates a ECSM ECC interrupt request as signalled by the assertion of
ESR[R1BC]. The address, attributes and data are also captured in the REAR, RESR, REMR, REAT and
REDR registers.
16-8
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor