PXD10RM Datasheet, PDF (121/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

4.2.6 Functional Description
The SWT is a 32-bit timer designed to enable the system to recover in situations such as software getting
trapped in a loop or if a bus transaction fails to terminate. It includes a a control register (SWT_CR), an
interrupt register (SWT_IR), time-out register (SWT_TO), a window register (SWT_WN), a service
register (SWT_SR) and a counter output register (SWT_CO).
The SWT_CR includes bits to enable the timer, set configuration options and lock configuration of the
module. The watchdog is enabled by setting the SWT_CR.WEN bit. The reset value of the
SWT_CR.WEN bit is 0 when exiting RESET mode if the flash user option bit 31 (WATCHDOG_EN) is
`0'. If the reset value of WATCHDOG_EN is 1, the SWT_CR.WEN bit is set and the watchdog starts
operation automatically after reset is released.
The SWT_TO register holds the watchdog time-out period in clock cycles unless the value is less than
0x100 in which case the time-out period is set to 0x100. This time-out period is loaded into an internal
32-bit down counter when the SWT is enabled and each time a valid service sequence is written. The
SWT_CR.CSL bit selects which clock (system or oscillator) is used to drive the down counter.
The configuration of the SWT can be locked through use of either a soft lock or a hard lock. In either case,
when locked the SWT_CR, SWT_TO and SWT_WN registers are read only. The hard lock is enabled by
setting the SWT_CR.HLK bit which can only be cleared by a reset. The soft lock is enabled by setting the
SWT_CR.SLK bit and is cleared by writing the unlock sequence to the service register. The unlock
sequence is a write of 0xC520 followed by a write of 0xD928 to the SWT_SR.WSC field. There is no
timing requirement between the two writes. The unlock sequence logic ignores service sequence writes
and recognizes the 0xC520, 0xD928 sequence regardless of previous writes. The unlock sequence can be
written at any time and does not require the SWT_CR.WEN bit to be set.
When enabled, the SWT requires periodic execution of the watchdog servicing sequence. The service
sequence is a write of 0xA602 followed by a write of 0xB480 to the SWT_SR.WSC field. Writing the
service sequence loads the internal down counter with the time-out period. There is no timing requirement
between the two writes. The service sequence logic ignores unlock sequence writes and recognizes the
0xA602, 0xB480 sequence regardless of previous writes. Accesses to SWT registers occur with no
peripheral bus wait states. (The peripheral bus bridge may add one or more system wait states.) However,
due to synchronization logic in the SWT design, recognition of the service sequence or configuration
changes may require up to three system plus seven counter clock cycles.
If window mode is enabled (SWT_CR.WND bit is set), the service sequence must be performed in the last
part of the time-out period defined by the window register. The window is open when the down counter is
less than the value in the SWT_WN register. Outside of this window, service sequence writes are invalid
accesses and generate a bus error or reset depending on the value of the SWT_CR.RIA bit. For example,
if the SWT_TO register is set to 5000 and SWT_WN register is set to 1000 then the service sequence must
be performed in the last 20% of the time-out period. There is a short lag in the time it takes for the window
to open due to synchronization logic in the watchdog design. This delay could be up to three system plus
four counter clock cycles.
The interrupt then reset bit (SWT_CR.ITR) controls the action taken when a time-out occurs. If the
SWT_CR.ITR bit is not set, a reset is generated immediately on a time-out. If the SWT_CR.ITR bit is set,
an initial time-out causes the SWT to generate an interrupt and load the down counter with the time-out
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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