PXD10RM Datasheet, PDF (1066/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

30.5.4 Power Saving Features
The QuadSPI supports three power-saving strategies:
• Stop Mode
• Module Disable Mode - Clock gating of non-memory mapped logic
• Clock gating of slave bus signals and clock to memory-mapped logic
Like all power saving features the Stop Mode requires logic external to the QuadSPI module for power
management and clock gating control. Figure 30-35 shows an example on how the QuadSPI power saving
features can be used:
Power
Management
Block
system clock
ipg_enable_clk
ipg_doze
ipg_stop_ack
ipg_stop
& ^ipg_clk
ips_addr,
ips_byte_en,
ips_rwb,
ips_wdata
&
&
&
&
Power Saving
Logic
Non-Memory Mapped Area
&
DOZE
MDIS
Memory Mapped Area
QuadSPI
ips_module_en
DQ
&
ipg_clk_s
Figure 30-35. QuadSPI module with Power Management Block
30.5.4.1 Stop Mode
The QuadSPI supports the global signal Stop Mode protocolusing the ipg_stop -> ipg_stop_ack
handshake. By default the ipg_stop_ack signal is de-asserted. When a request is made to enter Stop Mode,
the QuadSPI block acknowledges the request by asserting ipg_stop_ack when it is ready to have its clocks
shut off. Depending from the mode of operation the following conditions must be met for the assertion of
ipg_stop_ack:
• If a serial transfer is in progress in one of the SPI Modes the QuadSPI waits until it reaches the
frame boundary before asserting ipg_stop_ack.
• If a SFM command is currently executed in SFM Mode the assertion of the ipg_stop_ack is
postponed until this command is finished.
30-62
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor