PXD10RM Datasheet, PDF (427/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

dimension. The HEIGHT is limited to a maximum of 256 pixels, and the total number of pixels cannot
exceed the number of bits in the cursor RAM (8192 bits).
Bits in the cursor RAM that are 0 become transparent on the panel. Bits that are 1 become fully opaque in
the color defined in register 3 in the control descriptor for the cursor (CTRLDESCCURSOR_3). The
DEFAULT_CURSOR_COLOR bit field is in RGB888 format.
There are restrictions on the arrangement of bits in the cursor RAM depending on how the HEIGHT and
WIDTH bit fields are configured.
• The rightmost bit in the cursor RAM (bit 31) represents the leftmost pixel on the display.
• When the cursor size is less than 32 bits, each row of the cursor is contained in a single 32-bit word
of cursor RAM. The other bits in each row must be filled with zeros.
• When the cursor width is an integer multiple of 32 bits, the pixels in each row roll from one word
in the RAM to the next one. The rightmost bit in the first word in the RAM is the top leftmost pixel
on the display. The leftmost bit in the word represents a pixel that is adjacent to the rightmost bit
in the next word (in the same row). The leftmost pixel on the next row is the rightmost bit in the
first word after n words that describe the first row.
• When the cursor is greater than 32 bits but not an integer multiple of 32, the pixels in each row roll
from one word into the next one such that the rightmost bit in the first word of the row is the
leftmost bit on the display. In the final word of the row there are unused bits.
The position of the cursor on the panel is defined by register 2 in the control descriptor for the cursor
(CTRLDESCCURSOR _2). The register contains two bit fields, POSY and POSX, which determine the
location of the upper left pixel of the cursor in the x and y axes. Both fields are expressed in terms of the
number of pixels in each axis. Placing the cursor beyond the panel area is not allowed.
The cursor can be configured to blink at a particular rate when it is enabled. The EN_BLINK,
HWC_BLINK_ON, and HWC_BLINK_OFF bit fields define the blink behavior. These are in register 4
in the control descriptor for the cursor (CTRLDESCCURSOR_4). EN_BLINK enables blinking. The
blinking time is based on the frame rate, and the on and off times are independently configurable.
HWC_BLINK_ON configures the number of frame refresh cycles for which the cursor is visible.
HWC_BLINK_OFF configures the number of frame refresh cycles for which the cursor is not visible. For
a frame refresh rate of 64 Hz, the HWC_BLINK_ON and HWC_BLINK_OFF counters give a range of
on/off times up to 4 seconds.
The cursor is enabled by setting the CUR_EN bit field in register 3 in the control descriptor for the cursor
(CTRLDESCCURSOR_3). Visible pixels in the cursor graphic operate independently from the normal
layer blend process and always replace any other pixel at the same panel location. This has the effect of
making the cursor the highest priority layer on the panel when it is enabled and where it contains visible
pixels.
If the DCU detects an invalid configuration in the cursor control descriptor, then the cursor configuration
is invalid and it cannot be made visible. In addition, the error flag HWC_ERR is set in the layer parameter
error register (PARR_ERR).
The cursor RAM may be written at any time when the TFT LCD panel is not being driven with data. This
means that the RAM can be modified when the DCU is not enabled and during the vertical blanking period.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
12-95