PXD10RM Datasheet, PDF (157/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

5.4.9 Data registers
5.4.9.1 Introduction
ADC conversion results are stored in data registers. There is one register per channel.
The 0 to 31 range shown below is the maximum range for the channel type. For the exact number of
available channels, please refer to Table 5-5.
CDR[32..63] = Extended internal channels
CDR[64..95] = External channels
Each data register also gives information regarding the corresponding result as described below.
5.4.9.2 Channel Data Register (CDR[0..95])
Address: See Table 5-5
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0 _{VA OVER RESULT}
W
LID W
[0:1]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0
W
CDATA[0:9]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-26. Channel Data Register (CDR[0..95])
Table 5-24. Channel Data Register (CDR[0..95]) field descriptions
Field
0:11
12
13
Description
Reserved
Write of any value has no effect, read value is always 0.
VALID
Used to notify when the data is valid (a new value has been written). It is automatically cleared when
data is read.
OVERW: Overwrite data
This bit signals that the previous converted data has been overwritten by a new conversion. This
functionality depends on the value of MCR[OWREN]:
– When OWREN = 0, then OVERW is frozen to 0 and CDATA field is protected against being overwritten
until being read.
– When OWREN = 1, then OVERW flags the CDATA field overwrite status.
0 Converted data has not been overwritten
1 Previous converted data has been overwritten before having been read
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
5-35