PXD10RM Datasheet, PDF (893/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Offset MPU_Base + 0x010 (MPU_EAR0)
MPU_Base + 0x018 (MPU_EAR1)
MPU_Base + 0x020 (MPU_EAR2)
MPU_Base + 0x028 (MPU_EAR3)
Access: Read
Read
Read
Read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EADDR
W
Reset _{- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -}
Figure 24-3. MPU Error Address Register, Slave Port n (MPU_EARn)
Table 24-3. MPU_EARn Field Descriptions
Field
Description
0–31 Error Address. This read-only field is the reference address from slave port n that generated the access
EADDR error.
24.2.2.3 MPU Error Detail Register, Slave Port n (MPU_EDRn)
When the MPU detects an access error on slave port n, 32 bits of error detail are captured in this read-only
register and the corresponding bit in the MPU_CESR[SPERR] field set. Information on the faulting
address is captured in the corresponding MPU_EARn register at the same time. Note this register and the
corresponding MPU_EARn register contain the most recent access error; there are no hardware interlocks
with the MPU_CESR[SPERR] field as the error registers are always loaded upon the occurrence of each
protection violation.
Offset MPU_Base + 0x014 (MPU_EDR0)
MPU_Base + 0x01c (MPU_EDR1)
MPU_Base + 0x024 (MPU_EDR2)
MPU_Base + 0x02c (MPU_EDR3)
Access: Read
Read
Read
Read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EACD
R
EPID
EMN
EATTR
W
Reset _{- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -}
Figure 24-4. MPU Error Detail Register, Slave Port n (MPU_EDRn)
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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