PXD10RM Datasheet, PDF (618/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 17-49. ADR field descriptions (continued)
Field
Description
9:28 AD22-3: ADdress 22-3 (Read Only)
The Address Register provides the first failing address in the event of ECC error (MCR.EER set) or the
first failing address in the event of RWW error (MCR.RWE set), or the address of a failure that may have
occurred in a FPEC operation (MCR.PEG cleared). The Address Register provides also the first address
at which a ECC single error correction occurs (MCR.EDC set), if the SoC is configured to show this
feature.
The ECC double error detection takes the highest priority, followed by the RWW error, the FPEC error and
the ECC single error correction. When accessed ADR will provide the address related to the first event
occurred with the highest priority. The priorities between these 4 possible events is summarized in the
following table.
This address is always a Double Word address that selects 64 bits.
In case of a simultaneous ECC Double Error Detection on both Double Words of the same page, bit AD3
will output 0. The same is valid for a simultaneous ECC Single Error Correction on both Double Words of
the same page.
In User Mode the Address Register is read only.
29:31 Reserved (Read Only).
Write these bits has no effect and read these bits always outputs 0.
Priority Level
1
2
3
4
Table 17-50. ADR content: priority list
Error Flag
MCR.EER = 1
MCR.RWE = 1
MCR.PEG = 0
MCR.EDC = 1
ADR content
Address of first ECC Double Error
Address of first RWW Error
Address of first FPEC Error
Address of first ECC Single Error Correction
17.3.6.11 User Test 0 register (UT0)
Address Offset: 0x0003C
Reset value: 0x00000001
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
UTE
0
0
0
0
0
0
0
DSI7 DSI6 DSI5 DSI4 DSI3 DSI2 DSI1 DSI0
rw/0 r/0
r/0
r/0
r/0
r/0
r/0
r/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
X MRE MRV EIE AIS AIE AID
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 r/1
Figure 17-34. User Test 0 register (UT0)
The User Test feature gives the user of the Flash Module the ability to perform test features on the Flash.
The User Test 0 Register allows to control the way in which the Flash content check is done.
Bits MRE, MRV, AIS, EIE and DSI7-0 of the User Test 0 Register are not accessible whenever
MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
17-68
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor