PXD10RM Datasheet, PDF (1138/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

35.3.2.3 Motor Controller Period Register (MCPER)
Offset Module Base + 0x0002, 0x0003
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 0 0 0 0
W
PER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 35-4. Motor Controller Period Register (MCPER)
Table 35-6. MCPER Field Descriptions
Field
PER
Description
PWM Period — PER defines the number of motor controller timer counter clocks a PWM period lasts.
The motor controller timer counter is clocked with the frequency f_TC. If dither mode is enabled
(MCCTL0[DITH] = 1, refer to Section 35.4.1.3.5, Dither Bit (MCCTL0[DITH])”), PER[0] is ignored and
reads as a 0. In this case PER = 2 * MCDCx[DUTY[10:1]].
Setting PER to 0 will shut off all PWM channels as if MCCCx[MCAM] is set to 0 in all channel control
registers after the next period timer counter overflow. In this case, the motor controller releases all pins.
NOTE
Programming PER to 1 and setting the MCCTL0[DITH] bit will be
managed as if PER is programmed to 0. All PWM channels will be shut off
after the next period timer counter overflow.
35.3.2.4 Motor Controller Channel Control Register (MCCC0..11)
Each PWM channel has one associated control register to control output delay, PWM alignment, and
output mode. The number of each register refers directly the PWM channel it controls. The relation
between channels, pin names and register names is shown in Table 35-19.
Offset Module Base + 0x0010 . . . 0x001B
0
1
2
3
4
5
6
7
R
MCOM
W
0
0
MCAM
CD
Reset
0
0
0
0
0
0
0
0
Figure 35-5. Motor Controller Channel Control Register (MCCC0..11)
35-10
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor