PXD10RM Datasheet, PDF (388/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 12-33. Parameter Error Status Register field descriptions (continued)
Field
Description
20
Interrupt occurs whenever there is an error in layer 11.
L11_PARR_ERR 1’b0: Parameter error is not set
1’b1: Parameter error is set
21
Interrupt occurs whenever there is an error in layer 10.
L10_PARR_ERR 1’b0: Parameter error is not set
1’b1: Parameter error is set
22
L9_PARR_ERR
Interrupt occurs whenever there is an error in layer 9
1’b0: Parameter error is not set
1’b1: Parameter error is set
23
Interrupt occurs whenever there is an error in layer 8.
L08_PARR_ERR 1’b0: Parameter error is not set
1’b1: Parameter error is set
24
L7_PARR_ERR
Interrupt occurs whenever there is an error in layer 7
1’b0: Parameter error is not set
1’b1: Parameter error is set
25
L6_PARR_ERR
Interrupt occurs whenever there is an error in layer 6.
1’b0: Parameter error is not set
1’b1: Parameter error is set
26
L5_PARR_ERR
Interrupt occurs whenever there is an error in layer 5.
1’b0: Parameter error is not set
1’b1: Parameter error is set
27
L4_PARR_ERR
Interrupt occurs whenever there is an error in layer 4
1’b0: Parameter error is not set
1’b1: Parameter error is set
28
L3_PARR_ERR
Interrupt occurs whenever there is an error in layer 3.
1’b0: Parameter error is not set
1’b1: Parameter error is set
29
L2_PARR_ERR
Interrupt occurs whenever there is an error in layer 2.
1’b0: Parameter error is not set
1’b1: Parameter error is set
30
L1_PARR_ERR
Interrupt occurs whenever there is an error in layer 1.
1’b0: Parameter error is not set
1’b1: Parameter error is set
31
L0_PARR_ERR
Interrupt occurs whenever there is an error in layer 0.
1’b0: Parameter error is not set
1’b1: Parameter error is set
12.3.4.29 Mask PARR_ERR status register
Figure 12-39 shows the mask register for parameter error status register.
12-56
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor