PXD10RM Datasheet, PDF (492/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Name
NOP
CDNE[0:6]
Table 15-13. DMA Clear DONE Status (DMACDNE) field descriptions
Description
No Operation
Clear DONE Status Bit
Value
0 Normal operation.
1 No operation, ignore bits 6-0
0-63 Clear the corresponding channel’s DONE bit
64-127 Clear all TCD DONE bits
15.2.1.13 DMA Interrupt Request (DMAINTH, DMAINTL)
The DMAINT{H,L} registers provide a bit map for the implemented channels {16,32,64} signaling the
presence of an interrupt request for each channel. DMAINTH supports channels 63-32, while DMAINTL
covers channels 31-00. The DMA engine signals the occurrence of a programmed interrupt upon the
completion of a data transfer as defined in the transfer control descriptor by setting the appropriate bit in
this register. The outputs of this register are directly routed to the platform’s interrupt controller. During
the execution of the interrupt service routine associated with any given channel, it is software’s
responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write to the
DMACINT register in the interrupt service routine is used for this purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the DMACINT register. On writes to the DMAINT, a one in any bit position clears
the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding
channel’s current interrupt status. The DMACINT register is provided so the interrupt request for a single
channel can easily be cleared without the need to perform a read-modify-write sequence to the
DMAINT{H,L} registers. See Figure 15-14 and Table 15-14 for the DMAINT definition.
15-22
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor