PXD10RM Datasheet, PDF (624/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

17.3.6.17 User Multiple Input Signature Register 3 (UMISR3)
Address Offset: 0x00054
Reset value: 0x00000000
0
1
2
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4
5
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15
MS127 MS126 MS125 MS124 MS123 MS122 MS121 MS120 MS119 MS118 MS117 MS116 MS115 MS114 MS113 MS112
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
16
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MS111 MS110 MS109 MS108 MS107 MS106 MS105 MS104 MS103 MS102 MS101 MS100 MS099 MS098 MS097 MS096
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 17-40. User Multiple Input Signature Register 3 (UMISR3)
The Multiple Input Signature Register provides a mean to evaluate the Array Integrity.
The User Multiple Input Signature Register 3 represents the bits 127-96 of the whole 144 bits word (2
Double Words including ECC).
The UMISR3 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns
indeterminate data while writing has no effect.
Table 17-57. UMISR3 field descriptions
Field
Description
0:31 MS127-096: Multiple input Signature 127-096 (Read/Write)
These bits represent the MISR value obtained accumulating the bits 127-96 of all the pages read from the
Flash Memory.
The MS can be seeded to any value by writing the UMISR3 register.
17.3.6.18 User Multiple Input Signature Register 4 (UMISR4)
Address Offset: 0x00058
Reset value: 0x00000000
0
1
2
3
4
5
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MS159 MS158 MS157 MS156 MS155 MS154 MS153 MS152 MS151 MS150 MS149 MS148 MS147 MS146 MS145 MS144
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
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MS143 MS142 MS141 MS140 MS139 MS138 MS137 MS136 MS135 MS134 MS133 MS132 MS131 MS130 MS129 MS128
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 17-41. User Multiple Input Signature Register 4 (UMISR4)
The Multiple Input Signature Register provides a mean to evaluate the Array Integrity.
The User Multiple Input Signature Register 4 represents the ECC bits of the whole 144 bits word (2 Double
Words including ECC): bits 8-15 are ECC bits for the odd Double Word and bits 24-31 are the ECC bits
for the even Double Word; bits 4-5 and 20-21 of MISR are respectively the double and single ECC error
detection for odd and even Double Word.
17-74
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor