PXD10RM Datasheet, PDF (865/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

23.7.2.20 Identifier filter control register (IFCR2n)
This register is not implemented on LINFlex_1.
n = 0: Address: Base + 0x004C
n = 1: Address: Base + 0x0054
n = 2: Address: Base + 0x005C
n = 3: Address: Base + 0x0064
n = 4: Address: Base + 0x006C
n = 5: Address: Base + 0x0074
n = 6: Address: Base + 0x007C
n = 7: Address: Base + 0x0084
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0
W
DFL[0:2]
00
DIR CCS
ID[0:5]
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 23-26. Identifier filter control register (IFCR2n)
NOTE
This register can be written in Initialization mode only.
Table 23-28. IFCR2n field descriptions
Field
0:18
DFL[0:2]
19:21
DIR
22
CCS
23
24:25
ID[0:5]
26:31
Description
Reserved
Data Field Length
These bits define the number of data bytes in the response part of the frame.
Direction
This bit controls the direction of the data field.
0 LINFlex receives the data and copies them in the BDRL and BDRM registers.
1 LINFlex transmits the data from the BDRL and BDRM registers.
Classic Checksum
This bit controls the type of checksum applied on the current message.
0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN specification
2.0 and higher.
1 Classic Checksum covering Data fields only. This is compatible with LIN specification 1.3 and
earlier.
Reserved
Identifier
Identifier part of the identifier field without the identifier parity.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
23-33