PXD10RM Datasheet, PDF (312/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Refer to Section 11.8.7.4, Transmit FIFO Underflow Interrupt Request (TFUF), for details.
11.8.3.5 Receive First In First Out (RX FIFO) Buffering Mechanism
The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds four received
SPI data frames. SPI data is added to the RX FIFO at the completion of a transfer when the received data
in the shift register is transferred into the RX FIFO. SPI data is removed (popped) from the RX FIFO by
reading the DSPIx_POPR register. RX FIFO entries can only be removed from the RX FIFO by reading
the DSPIx_POPR or by flushing the RX FIFO.
Refer to Section 11.7.2.7, DSPI POP RX FIFO Register (DSPIx_POPR) for more information on the
DSPIx_POPR.
The RX FIFO counter field (RXCTR) in the DSPI status register (DSPIx_SR) indicates the number of
valid entries in the RX FIFO. The RXCTR is updated every time the DSPI _POPR is read or SPI data is
copied from the shift register to the RX FIFO.
The POPNXTPTR field in the DSPIx_SR points to the RX FIFO entry that is returned when the
DSPIx_POPR is read. The POPNXTPTR contains the positive, 32-bit word offset from DSPIx_RXFR0.
For example, POPNXTPTR equal to two means that the DSPIx_RXFR2 contains the received SPI data
that is returned when DSPIx_POPR is read. The POPNXTPTR field is incremented every time the
DSPIx_POPR is read. POPNXTPTR rolls over every four frames on the MCU.
11.8.3.5.1 Filling the RX FIFO
The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full,
SPI frames from the shift register are transferred to the RX FIFO. Every time an SPI frame is transferred
to the RX FIFO the RX FIFO counter is incremented by one.
If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the DSPIx_SR is set
indicating an overflow condition. Depending on the state of the ROOE bit in the DSPIx_MCR, the data
from the transfer that generated the overflow is ignored or put in the shift register. If the ROOE bit is set,
the incoming data is put in the shift register. If the ROOE bit is cleared, the incoming data is ignored.
11.8.3.5.2 Draining the RX FIFO
Host software or the eDMA can remove (pop) entries from the RX FIFO by reading the DSPIx_POPR. A
read of the DSPIx_POPR decrements the RX FIFO counter by one. Attempts to pop data from an empty
RX FIFO are ignored, the RX FIFO counter remains unchanged. The data returned from reading an empty
RX FIFO is undetermined.
Refer to Section 11.7.2.7, DSPI POP RX FIFO Register (DSPIx_POPR) for more information on
DSPIx_POPR.
When the RX FIFO is not empty, the RX FIFO drain flag (RFDF) in the DSPIx_SR is set. The RFDF bit
is cleared when the RX_FIFO is empty and the eDMA controller indicates that a read from DSPIx_POPR
is complete; alternatively the RFDF bit can be cleared by the host writing a 1 to it.
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor