PXD10RM Datasheet, PDF (273/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

PRE SCALED CLOCK RATIO = 1 (bypassed)
system clock
input event/prescaler clock enable = 1
see note 1
internal counter 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
match value = 3
FLAG set event
FLAG pin/register
FLAG clear
Note 1: When a match occurs, the first clock cycle is used to
clear the internal counter, starting another period.
Figure 9-42. Time base period when running in the fastest prescaler ratio
If the prescaler ratio is greater than one or external clock is selected, the counter may behave in three
different ways depending on the channel mode:
• If MC mode and Clear on Match Start and External Clock source are selected the internal counter
behaves as described in Figure 9-43.
• If MC mode and Clear on Match Start and Internal Clock source are selected the internal counter
behaves as described in Figure 9-44.
• If MC mode and Clear on Match End are selected the internal counter behaves as described in
Figure 9-45.
• If OPWFM mode is selected the internal counter behaves as described in Figure 9-44. The internal
counter clears at the start of the match signal, skips the next prescaled clock edge and then
increments in the subsequent prescaled clock edge.
NOTE
MCB and OPWFMB modes have a different behavior.
system clock
input event
internal counter
1
2
3
0
1
2
3
0
1
2
match value = 3
see note 1
FLAG set event
FLAG pin/register
FLAG clear
Note 1: When a match occurs, the first system clock cycle is used to clear the
internal counter, and at the next edge of prescaler clock enable
the counter will start counting.
Figure 9-43. Time base generation with external clock and clear on match start
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-47