PXD10RM Datasheet, PDF (1121/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

signal1
signal2
signal3
signal4
signal1: Signal with fixed duty cycle and variable frequency
signal2: TONE Signal with fixed frequency (Refer to falling edges) and variable duty cycle
signal3: Anded output (sound_out) of Signal1 and Signal2 coming from the mixer
signal4: sound_out after passing through the low pass filter (external to the SGL)
Figure 33-9. Monotonic sound generation
• Polyphonic sound
For polyphonic sound, PCM coded samples which reside in system memory, are loaded into the
PWM registers at the PCM sample frequency(for example, 16 kHz). So, for a given time period
(1/16 kHz), the PWM output has a fixed duty cycle and frequency. A new sample is loaded into the
PWM register (at the rate of 16 kHz), which results in a corresponding change in the duty cycle
and frequency (both of which will remain fixed until the loading of new PCM coded sample). The
resulting PWM signal gives polyphonic sound as an output. The output must be filtered by a
low-pass filter. The quality and the order of the low-pass filter will have a direct impact on the
quality of the produced sound.
The SGL takes outputs of the 16 PWM channels being used for sound generation as inputs and processes
them accordingly, depending on whether monotonic or polyphonic sound is to be generated, to give
sound_out as the output signal.
The select lines for multiplexers come from a register (MODE_SEL) which is configured by software.
The type of sound output (monotonic or polyphonic) is controlled by MODE_SEL[M_P]. The value of
MODE_SEL[SOUND_CTRL] determines the duration of sound and whether the sound output is periodic
or continuous.
Each duration register (HIGH_PERIOD, LOW_PERIOD and SOUND_DURATION) has a total size of
32 bits. The clock on which their counters operate is provided by a programmable prescaler
(MODE_SEL[PRE] can be configured to divide clk by values as shown in Figure 33-1), so that the
duration for which sound can be produced becomes significant.
The fixed prescaler brings down the time base at 64 MHz system clock frequency to 1 microsecond, which
can be further prescaled by using the programmable prescaler.
The HIGH_PERIOD, LOW_PERIOD and SOUND_DURATION registers must be reprogrammed each
time sound needs to be generated, with a new configuration of MODE_SEL[SOUND_CTRL].
See Table 33-9 for a detailed description of how the SOUND_CTRL bits affect the generated sound.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
33-7