PXD10RM Datasheet, PDF (860/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

23.7.2.14 Buffer identifier register (BIDR)
Address: Base + 0x0034
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
R
W
Reset 0
Field
0:15
DFL[0:5]
16:21
DIR
22
CCS
23
24:25
ID[0:5]
26:31
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DFL[0:5]
00
DIR CCS
ID[0:5]
000000000000000
Figure 23-20. Buffer identifier register (BIDR)
Table 23-20. BIDR field descriptions
Description
Reserved
Data Field Length
These bits define the number of data bytes in the response part of the frame.
DFL[0:5] = Number of data bytes – 1.
Normally, LIN uses only DFL[0:2] to manage frames with a maximum of 8 bytes of data. Identifier
filters are compatible with DFL[0:2] only. DFL[3:5] are provided to manage extended frames.
Direction
This bit controls the direction of the data field.
0 LINFlex receives the data and copies them in the BDR registers.
1 LINFlex transmits the data from the BDR registers.
Classic Checksum
This bit controls the type of checksum applied on the current message.
0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN
specification 2.0 and higher.
1 Classic Checksum covering Data fields only. This is compatible with LIN specification 1.3 and
earlier.
In LIN slave mode (MME bit cleared in LINCR1), this bit must be configured before the header
reception. If the slave has to manage frames with 2 types of checksum, filters must be configured.
Reserved
Identifier
Identifier part of the identifier field without the identifier parity.
23-28
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor