PXD10RM Datasheet, PDF (665/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

hclk
htrans
haddr, hprot
hwrite
hrdata
hwdata
hready_out
hresp
bkn_fl_addr
bkn_fl_rd_en
bkn_fl_wr_en
bkn_fl_rdata
bkn_fl_xfr_err
bkn_done
bkn_abort
ECSM_mir[fbnsi]
ECSM_mir[fbnai]
1
2
nonseq
addr y
Burst Read, Stall-and-Retry, APC=2, RWSC=2, PFLM=2
3
4
5
6
7
8
seq
addr y+4
okay okay okay
y
y+16
addr y
okay okay
okay
y
okay okay
y+16
addr y (retry)
9
10
seq
addr y+8
C(y)
C(y+4)
okay okay
addr y+16
C(y)
Figure 17-51. 3-Cycle Access, Stall-and-Retry with Bn_RWWC = 11x
As shown in Figure 17-51, the 3-cycle access to address y is interrupted when an operation causes the
bkn_done signal to be negated signaling that the array bank is busy with a high-voltage program or erase
event. Eventually, this array operation completes (at the end of cycle 4) and bkn_done returns to a logical
1. In cycle 6, the PFLASH2P_LCA module retries the read to address y which was interrupted by the
negation of bkn_done in cycle 3. Note that throughout cycles 2-9, the AHB bus pipeline is stalled with a
read to address y in the AHB data phase and a read to address y+4 in the address phase. Depending on the
state of the least-significant-bit of the Bn_RWWC control field, the hardware may also signal a stall
notification interrupt (if Bn_RWWC = 110). The stall notification interrupt is shown as the optional
assertion of ECSM’s MIR[FBnSI] (flash bank n stall interrupt).
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
17-115