PXD10RM Datasheet, PDF (720/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

19.6 External signal description
The JTAGC consists of four signals that connect to off-chip development tools and allow access to test
support functions. The JTAGC signals are outlined in Table 19-1.
Table 19-1. JTAG signal properties
Name
TCK
TDI
TDO
TMS
I/O
Function
I
Test clock
I
Test data in
O
Test data out
I
Test mode select
Reset State
Pull Up
Pull Up
High Z
Pull Up
All 4 JTAG pins (TCK/TMS/TDI/TDO) are shared with GPIO pins, so that the software may configure
these pins as input/output by programming the appropriate registers.
To ensure the proper working of JTAG, these registers have a reset value such that these pins behave as
JTAG pins when the POR is lifted:
• TDI : input/pull-up
• TCK : Input/pull-up
• TMS : input/pull-up
• TDO : high-Z/pull-disabled
On entry to STANDBY mode the TDO pin goes to the high-Z/pull-disabled state. Some external debugger
connections may expect the TDO to be in a known state during standby so an external pull up or down may
be required for correct operation when debugging STANDBY.
19.7 Memory map and register description
This section provides a detailed description of the JTAGC registers accessible through the TAP interface,
including data registers and the instruction register. Individual bit-level descriptions and reset states of
each register are included. These registers are not memory-mapped and can only be accessed through the
TAP.
19.7.1 Instruction Register
The JTAGC uses a 5-bit instruction register as shown in Figure 19-2. The instruction register allows
instructions to be loaded into the module to select the test to be performed or the test data register to be
accessed or both. Instructions are shifted in through TDI while the TAP controller is in the Shift-IR state,
and latched on the falling edge of TCK in the Update-IR state. The latched instruction value can only be
changed in the update-IR and test-logic-reset TAP controller states. Synchronous entry into the
test-logic-reset state results in the IDCODE instruction being loaded on the falling edge of TCK.
Asynchronous entry into the test-logic-reset state results in asynchronous loading of the IDCODE
instruction. During the capture-IR TAP controller state, the instruction shift register is loaded with the
value 0b10101, making this value the register’s read value when the TAP controller is sequenced into the
Shift-IR state.
19-4
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor