PXD10RM Datasheet, PDF (371/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Offset: 0x1E4
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17.
Figure 12-20. SYN_POL Register
Table 12-22. SYN_POL field descriptions
Field
21
INV_PDI_DE
22
INV_PDI_HS
23
INV_PDI_VS
24
INV_PDI_CLK
25
INV_PXCK
26
NEG
27
BP_VS
28
BP_HS
Description
Polarity change of PDI input data Enable.
1’b0: DE is active high
1’b1: DE is active low
Polarity change of PDI input HSYNC.
1’b0: HSYNC is active high
1’b1: HSYNC is active low
Polarity change of PDI input VSYNC.
1’b0: VSYNC is active high
1’b1: VSYNC is active low
Polarity change of PDI input Clock.
1’b0: DCU samples data on the rising edge
1’b1: DCU samples data on the falling edge
Polarity change of Pixel Clock.
1’b0: Display samples data on the falling edge
1’b1: Display samples data on the rising edge
Indicates if value at the output (pixel data output) needs to be negated.
1’b0: Output is to remain same
1’b1: Output to be negated
Bypass Vertical Synchronize Signal (internal pin muxing).
1’b0: Do not bypass VSYNC signal output
1 ‘b1: CSYNC bypass VSYNC signal, output CSYNC instead of VSYNC
Bypass Horizontal Synchronize Signal (internal pin muxing).
1’b0: Do not bypass HSYNC signal output
1’b1: CSYNC bypass HSYNC signal, output CSYNC instead of HSYNC
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
12-39