PXD10RM Datasheet, PDF (372/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Field
29
INV_CS
30
INV_VS
31
INV_HS
Table 12-22. SYN_POL field descriptions (continued)
Description
Invert Composite Synchronize Signal.
1’b0: Not invert CSYNC signal, active HIGH
1 ‘b1: Invert CSYNC signal, active LOW
Invert Vertical Synchronize Signal
1’b0: Not invert VSYNC signal, active HIGH
1 ‘b1: Invert VSYNC signal, active LOW
Invert Horizontal Synchronize Signal.
1’b0: Not invert HSYNC signal, active HIGH
1’b1: Invert HSYNC signal, active LOW
12.3.4.18 Threshold Register
Figure 12-21 represents the Threshold Register.
Offset: 0x1E8
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0 0 0
W
LS_BF_VS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
OUT_BUF_HIGH
W
OUT_BUF_LOW
Reset 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0
Figure 18.
Figure 12-21. Threshold Register
Table 12-23. Threshold Register Field Descriptions
Field
Description
6–15
LS_BF_VS
Lines before VSYNC threshold value. The LS_BF_VS status flag (in INT_STATUS) is set this
number of lines before the VSYNC signal is asserted.
16–23
Output buffer high threshold (in pixels). When the output buffer exceeds this value the datapath
OUT_BUF_HIGH clock is suspended.
24–31
Output buffer filling low Threshold (in pixels).This value is used to generate the underrun
OUT_BUF_LOW exception (UNDRUN in INT_STATUS).
12.3.4.19 Interrupt Status Register (INT_STATUS)
Figure 12-22 indicates the interrupt status register. See Section 12.5.4, Interrupt generation,” for a
description of how the DCU collects interrupt events into different source groups.
12-40
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor