PXD10RM Datasheet, PDF (112/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Note that in this case the write enable SLBRn.WE[0] must be set while SLBRn.WE[1] does not matter. As
the enable bits SLBRn.WE[3:2] are cleared the lock bits SLBRn.SLB[3:2] remain unchanged.
In the example on the left side of Figure 4-7 the data written to SLBRn.SLB[0] is mirrored to
SLBRn.SLB[1] and the data written to SLBRn.SLB[2] is mirrored to SLBRn.SLB[3] as for both registers
the write enables are set.
In Figure 4-8 a 32-bit wise protected register is shown. When SLBRn.WE[0] is set the data written to
SLBRn.SLB[0] is automatically written to SLBRn.SLB[3:1] also. Otherwise SLBRn.SLB[3:0] remains
unchanged.
to SLB0 to SLB1 to SLB2 to SLB3 write data
1
X
X
X SLBRn.WE[3:0]
update lock bits
SLB0 SLB1 SLB2 SLB3 SLBR.SLB[3:0]
Figure 4-8. Change Lock Settings for 32-bit Protected Addresses
In Figure 4-9 an example is shown which has a mixed protection size configuration:
to SLB0 to SLB1 to SLB2 to SLB3 write data
1
X
X
1 SLBRn.WE[3:0]
update lock bits
SLB0 SLB1 0 SLB3 SLBR
Figure 4-9. Change Lock Settings for Mixed Protection
The data written to SLBRn.SLB[0] is mirrored to SLBRn.SLB[1] as the corresponding register is 16-bit
protected. The data written to SLBRn.SLB[2] is blocked as the corresponding register is unprotected. The
data written to SLBRn.SLB[3] is written to SLBRn.SLB[3].
4.1.4.2.2 Enable Locking Via Mirror Module Space (Area #3)
It is possible to enable locking for a register after writing to it. To do so the mirrored module address space
must be used. Figure 4-10 shows one example:
PXD10 Microcontroller Reference Manual, Rev. 1
4-8
Freescale Semiconductor
Preliminary—Subject to Change Without Notice