PXD10RM Datasheet, PDF (943/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

All power domains except power domains #0 and #1 are configurable in this mode. Active power domains
are determined by the power configuration register PCU_PCONF2 of the MC_PCU.
NOTE
As flash modules can be configured to a low-power or power-down state in
these modes, software must ensure that the code will execute from RAM
before it changes to this mode.
25.4.2.5 RUN0…3 Modes
The device enters one of these modes on the following events:
• from the DRUN another RUN0…3 mode when the TARGET_MODE bit field of the ME_MCTL
register is written with “0100…0111”
• from the HALT mode by an interrupt event
• from the STOP mode by an interrupt or wakeup event
As soon as any of the above events occur, a RUN0…3 mode transition request is generated. The mode
configuration information for these modes is provided by ME_RUN0…3_MC registers. In these modes,
the flashes, all clock sources, and the system clock configuration can be controlled by software as required.
These modes are intended to be used by software
• to execute application routines
All power domains except power domains #0 and #1 are configurable in these modes in order to reduce
leakage consumption. Active power domains are determined by the power configuration register
PCU_PCONF2 of the MC_PCU.
NOTE
As flash modules can be configured to a low-power or power-down state in
these modes, software must ensure that the code will execute from RAM
before it changes to this mode.
25.4.2.6 HALT Mode
The device enters this mode on the following events:
• from one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register
is written with “1000”.
As soon as any of the above events occur, a HALT mode transition request is generated. The mode
configuration information for this mode is provided by ME_HALT_MC register. This mode is quite
configurable, and the ME_HALT_MC register should be programmed according to the system needs. The
flashes can be put in power-down mode as needed. If there is a HALT mode request while an interrupt
request is active, the device mode does not change, and an invalid mode interrupt is not generated.
This mode is intended as a first level low-power mode with
• the core clock frozen
• only a few peripherals running
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
25-37