PXD10RM Datasheet, PDF (1017/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 30-9. QSPI_MCR Field Descriptions (continued)
Field
Description
PCSSE
Peripheral Chip Select Strobe Enable. Only applicable if QMODE is cleared. The PCSSE bit
enables the PCS[5]/PCSS to operate as an PCS Strobe output signal. See Section 30.5.2.7.5,
Peripheral Chip Select Strobe Enable (PCSS),” for more information.
0 PCS5/PCSS is used as the Peripheral Chip Select[5] signal
1 PCS5/PCSS is used as an active-low PCS Strobe signal
ROOE
RX FIFO Overflow Overwrite Enable. Only applicable if QMODE is cleared. The ROOE bit enables
an RX FIFO overflow condition to either ignore the incoming serial data or to overwrite existing data.
If the RX FIFO is full and new data is received, the data from the transfer that generated the overflow
is either ignored or shifted in to the shift register. If the ROOE bit is asserted, the incoming data is
shifted in to the shift register. If the ROOE bit is negated, the incoming data is ignored. See
Section 30.5.2.10.6, RX FIFO Overflow Interrupt Request,” for more information.
0 Incoming data is ignored
1 Incoming data is shifted in to the shift register
PCSISx
Peripheral Chip Select Inactive State. Only applicable if QMODE is cleared. The PCSIS bit
determines the inactive state of the PCSx signal.
0 The inactive state of PCSx is low
1 The inactive state of PCSx is high
DOZE
Doze Enable. The DOZE bit provides support for externally controlled Doze Mode power-saving
mechanism. See Section 30.5.4, Power Saving Features,” for details.
0 A doze request will be ignored by the QuadSPI module
1 A doze request will be processed by the QuadSPI module
MDIS
Module Disable. The MDIS bit allows the clock to be stopped to the non-memory mapped logic in the
QuadSPI effectively putting the QuadSPI in a software controlled power-saving state. See
Section 30.5.4, Power Saving Features” and Section 30.5.2.1, Start and Stop of SPI Transfers” for
more information.
0 Enable QuadSPI clocks.
1 Allow external logic to disable QuadSPI clocks.
DIS_TXF
Disable TX FIFO. Only applicable if QMODE is cleared. The DIS_TXF bit provides a mechanism
to disable the TX FIFO. When the TX FIFO is disabled, the transmit part of the QuadSPI operates as
a simplified double-buffered SPI. See Section 30.5.2.4, FIFO Disable Operation,” for details.
0 TX FIFO is enabled
1 TX FIFO is disabled
DIS_RXF
Disable RX FIFO. Only applicable if QMODE is cleared. The DIS_RXF bit provides a mechanism
to disable the RX FIFO. When the RX FIFO is disabled, the receive part of the QuadSPI operates as
a simplified double-buffered SPI. See Section 30.5.2.4, FIFO Disable Operation,” for details.
0 RX FIFO is enabled
1 RX FIFO is disabled
CLR_TXF
Clear TX FIFO/Buffer. Depending from the QMODE bit CLR_TXF is used to invalidate the TX FIFO
or the TX Buffer content.
0 No action
1 (QMODE bit cleared): Read and write pointers of RX FIFO are reset to 0. QSPI_SPISR[TXCTR]
and QSPI_SPISR[TXNXTPTR] are reset to 0.
1 (QMODE bit set): Read and write pointers of the RX Buffer are reset to 0. QSPI_TBSR[TRCTR]
is reset to 0.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-13