PXD10RM Datasheet, PDF (132/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

NOTE
If the higher threshold for the analog watchdog is programmed lower than
the lower threshold and the converted value is less than the lower threshold,
then the WDGxL interrupt for the low threshold violation is set, else if the
converted value is greater than the lower threshold (consequently also
greater than the higher threshold) then the interrupt WDGxH for high
threshold violation is set. Thus, the user should avoid that situation as it
could lead to misinterpretation of the watchdog interrupts.
5.3.5 DMA functionality
A DMA request can be programmed after the conversion of every channel by setting the respective
masking bit in the DMAR registers. The DMAR masking registers must be programmed before starting
any conversion. There is one DMAR per channel type.
The DMA transfers can be enabled using the DMAEN bit of DMAE register. When the DCLR bit of
DMAE register is set then the DMA request is cleared on the reading of the register for which DMA
transfer has been enabled.
5.3.6 Interrupts
The ADC generates the following maskable interrupt signals:
• ADC_EOC interrupt requests
— EOC (end of conversion)
— ECH (end of chain)
— JEOC (end of injected conversion)
— JECH (end of injected chain)
• WDGxL and WDGxH (watchdog threshold) interrupt requests
Interrupts are generated during the conversion process to signal events such as End Of Conversion as
explained in register description for CEOCFR. Two 7-bit registers named CEOCFR (Channel Pending
Registers) and IMR (Interrupt Mask Register) are provided in order to check and enable the interrupt
request to EIC module.
Interrupts can be individually enabled on a channel by channel base by programming the CIMR (Channel
Interrupt Mask Register).
Several Channel Interrupt Pending Registers are also provided in order to signal which of the channels’
measurement has been completed.
The analog watchdog interrupts are handled by two 8-bit registers WTISR (Watchdog Threshold Interrupt
Status Register) and WTIMR (Watchdog Threshold Interrupt Mask Register) in order to check and enable
the interrupt request to the EIC module. The Watchdog interrupt source sets two pending bits WDGxH and
WDGxL in the WTISR for each of the four channels being monitored.
5-10
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor