PXD10RM Datasheet, PDF (370/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Offset: 0x1E0
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0
W
BP_V
00
PW_V[0:3]
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
16
R
W
Reset 0
Field
1–9
BP_V
12–20
PW_V
23–31
FP_V
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PW_V[4:8]
00
FP_V
001100000000011
Figure 16.
Figure 12-19. VSYN_PARA Register
Table 12-21. VSYN_PARA Field Descriptions
Description
VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of
1.
VSYNC active pulse width (in horizontal line cycles).
VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of
1.
12.3.4.17 SYN_POL Register
Figure 12-20 represents the SYN_POL register. SYN_POL register selects polarity for corresponding
synchronize signals (HSYNC, VSYNC, CSYNC), and controls the bypass of HSYNC or VSYNC with
CSYNC signal.
12-38
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor