PXD10RM Datasheet, PDF (1156/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

35.4.1.3.5 Dither Bit (MCCTL0[DITH])
The purpose of the dither mode is to increase the minimum length of output pulses without decreasing the
PWM resolution, in order to limit the pulse distortion introduced by the slew rate control of the outputs. If
dither mode is selected the output pattern will repeat after two timer counter overflows. For the same
output frequency, the shortest output pulse will have twice the length while dither feature is selected. To
achieve the same output frame frequency, the prescaler of the SMC module has to be set to twice the
division rate if dither mode is selected; e.g., with the same prescaler division rate the repeat rate of the
output pattern is the same as well as the shortest output pulse with or without dither mode selected.
The MCCTL0[DITH] bit enables or disables the dither function.
MCCTL0[DITH] = 0: dither function is disabled.
When MCCTL0[DITH] is cleared and assuming left aligned operation and MCCTL1[RECIRC] = 0, the
PWM output will start at a logic low level at the beginning of the PWM period (motor controller timer
counter = 0x000). The PWM output remains low until the motor controller timer counter matches the
11-bit PWM duty cycle value MCDCx[DUTY]. When a match (output compare between motor controller
timer counter and MCDCx[DUTY]) occurs, the PWM output will toggle to a logic high level and will
remain at a logic high level until the motor controller timer counter overflows (reaches the contents of
MCPER[PER] – 1). After the motor controller timer counter resets to 0x000, the PWM output will return
to a logic low level. This completes one PWM period. The PWM period repeats every MCPER[PER]
counts of the motor controller timer counter. If MCDCx[DUTY] >= MCPER[PER], the output will be
static low. If MCDCx[DUTY] = 0, the output will be continuously at a logic high level. The relationship
between the motor controller timer counter clock, motor controller timer counter value, and PWM output
while MCCTL0[DITH] = 0 is shown in Figure 35-27.
Motor Controller
Timer Counter Clock
Motor Controller
Timer Counter
0
100 199 0
100
199 0
PWM Output
1 Period
200 Counts
1 Period
200 Counts
Figure 35-27. PWM Output: MCCTL0[DITH] = 0, MCCCx[MCAM] = 0x1, MCDCx[DUTY] = 100,
MCPER[PER] = 200, MCCTL1[RECIRC] = 0
MCCTL0[DITH] = 1: dither function is enabled
Please note if MCCTL0[DITH] = 1, the bit MCPER[PER[0]] will be internally forced to 0 and read always
as 0.
When MCCTL0[DITH] is set and assuming left aligned operation and MCCTL1[RECIRC] = 0, the PWM
output will start at a logic low level at the beginning of the PWM period (when the motor controller timer
counter = 0). The PWM output remains low until the motor controller timer counter matches the 10-bit
35-28
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor