PXD10RM Datasheet, PDF (929/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

25.3.2.9 TEST Mode Configuration Register (ME_TEST_MC)
Address 0xC3FD_C024
Access: Supervisor read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
PDO
DFLAON CFLAON
W
Reset 0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
SYSCLK
W
Reset 0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Figure 25-10. TEST Mode Configuration Register (ME_TEST_MC)
This register configures system behavior during TEST mode. Please refer to Table 25-11 for details.
NOTE
Byte and half-word write accesses are not allowed to this register.
25.3.2.10 SAFE Mode Configuration Register (ME_SAFE_MC)
Address 0xC3FD_C028
Access: Supervisor read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
PDO
DFLAON CFLAON
W
Reset 0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
SYSCLK
W
Reset 0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Figure 25-11. SAFE Mode Configuration Register (ME_SAFE_MC)
This register configures system behavior during SAFE mode. Please refer to Table 25-11 for details.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
25-23