PXD10RM Datasheet, PDF (548/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Register address: ECSM Base +0x6c
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
REDR[0:15]
W
RESET: x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
REDR[16:31]
W
RESET: x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
= Unimplemented
Figure 16-18. RAM ECC Data (REDR) Register
Table 16-20. RAM ECC Data (REDR) Field Descriptions
Name
0-31
REDR[0:31]
Description
RAM ECC Data Register
This 32-bit register contains the data associated with the faulting access of the last,
properly-enabled RAM ECC event. The register contains the data value taken directly from the
data bus.
16.4.3 High Priority Enables
e200 processors can be configured to support critical and/or external interrupts. Furthermore, each
processor can be configured to employ priority elevation on critical and/or external interrupt events.
Critical interrupts come from outside the platform, and are routed directly to the processor’s critical
interrupt input. External interrupts are routed through the interrupt controller. In addition to the interrupt
notification signals, various processor-specific configuration flags from the processor’s Machine Check
Register (MCR[ee,ce]) and the Hardware Implementation Register (HID1) are sent to the ECSM to
determine when interrupt servicing is enabled and when high-priority elevation should be enabled. If the
corresponding processor is configured to allow high-priority elevation on critical interrupt events, the
ECSM generates the high-priority signal upon critical interrupt detection and holds it active throughout
the duration of interrupt servicing. If the corresponding processor is configured to allow high-priority
elevation on external interrupt events, the ECSM generates the high-priority signal upon external interrupt
detection and holds it active throughout the duration of interrupt servicing. During interrupt servicing the
processor status output, p_stat, is monitored for indication of a return from interrupt (rfi).
Great care needs to be taken when using the priority elevation as it can enable a master to starve the rest
of the masters in the system. Please see Chapter 10, Crossbar Switch (XBAR),” for information on priority
elevation.
16-22
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor