PXD10RM Datasheet, PDF (549/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

16.4.4 Spp_ips_reg_protection
The spp_ips_reg_protection logic provides hardware enforcement of supervisor mode access protection
for five on-platform IPS modules: INTC, ECSM, MPU, STM, and SWT. This logic resides between the
on-platform bus sourced by the AIPS bus controller and the individual slave modules. It monitors the bus
access type (supervisor or user) and if a user access is attempted, the transfer is terminated with an error
and inhibited from reaching the slave module. Identical logic is replicated for each of the five, targeted
slave modules. A block diagram of the spp_ips_reg_protection module is shown in Figure 16-19.
ips_xfr_wait[0]
ips_xfr_err[0]
qual_ips_mod_en[0]
INTC
ips_supervisor_access
ips_module_en[4:0]
ips_xfr_wait[1]
ips_xfr_err[1]
qual_ips_mod_en[1]
final_ips_xfr_wait[4:0]
AIPS_LITE _{final_ips_xfr_err[4:0]}
SPP_IPS_REG_PROTECTION
ips_xfr_wait[2]
ips_xfr_err[2]
qual_ips_mod_en[2]
ECSM
MPU
ips_xfr_wait[3]
ips_xfr_err[3]
qual_ips_mod_en[3]
STM
ips_xfr_wait[4]
ips_xfr_err[4]
qual_ips_mod_en[4]
Figure 16-19. Spp_Ips_Reg_Protection Block Diagram
SWT
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
16-23