PXD10RM Datasheet, PDF (1187/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

For proper usage of the SSD block it must have exclusive control over the coils belonging to the
SM whose stall position must be detected. This must be ensured at the device level. Following this
the SSD must be enabled by setting the RTZE bit in the CONTROL register, this bit must be left
asserted for the complete SSD flow.
It is at this point in time that application-dependent control settings are set which remain constant
over the complete SSD flow. These settings consist of the integrate direction of the ITGACC
register, which is set by the ITGDIR bit and the direction to advance the STEP setting (increment
or decrement influence clockwise or counter-clockwise movement of the SM). Additionally the
PRESCALE and the IRQ register must be programmed (it is not recommended to change the
content of the PRESCALE register during a running BIS).
2. Initialize SSD
At this point the STEP bits are set according to the angular position of the SM for the current
position. After programming the STEP bits the analog block can be enabled by setting the SDCPU
bit.
3. Start Blanking
This step starts with setting the TRIG bit together with the STEP bits initializing the complete BIS
for the next step. Depending from the direction of the rotation the previous step setting is either
decremented or incremented, wrapping from 2’b11 to 2’b00 or vice versa. If the BLNDCL bit is
set this step marks the start of the SM movement, During blanking both pins of the non-driven coil
are connected either to VDDM or VSSM for recirculation, depending from the RCIR bit. The bus
clock is divided accordingly to the BLNDIV bits to decrement the DCNT. The BLNST bit is set to
allow the user to monitor the status.
4. End of Blanking?
The end of the blanking phase is automatically detected. If the DCNT reaches 0x0000 and the
complete blanking time is expired the BLNIF flag is set and the interrupt triggered according to the
BLNIE bit. The BLNST bit is cleared.
5. Start Integration
After the end of the blanking phase the SSD block continues automatically with the integration
phase:
The ITGCNTLD register is used to initialize the DCNT and is decremented according to the
ITGDIV bits setting. The driving coils is powered according to the ITGDCL bit. During the
integration phase the polarity flip for offset cancellation is triggered according to the OFFCNC bits.
The ITGST bit is set to allow the user to monitor the status.
6. End of Integration?
The down counter is monitored in the same way like in step 4. The ITGIF flag is set and the
interrupt is triggered according to the ITGIE bit. The ITGST bit is cleared.
7. Stop Integration
On the expiration of the current BIS the integration is stopped, the -modulator is disabled, the
ITGACC register is frozen. Note that the current to the coil driven by the SSD block continues
according to the ITGDCL and the STEP setting.
8. Read Integration Result
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
36-21