PXD10RM Datasheet, PDF (1176/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 36-9. ITGCNTLD Register Field Description
Field
Description
15-0
ITGCNTLD - Integration Count Load value. This register is programmed with the number of down counter
periods belonging to the integration phase of the following BISs. Number format is unsigned. Refer to the
Functional Description of the integrator for further details.
Programming all 0’s into the ITGCNTLD register bits disables integration completely.
36.3.3.7 SSD Prescale and Divider Register (PRESCALE)
Figure 36-9 below describes the fields of the prescale and divider factor (PRESCALE) register:
Offset 0x0C
15 14
13
12 11 10
9
8
R
0
BLNDIV
ITGDIV
W
Reset 0 0
0
000
0
0
Access: User read/write
76
5
4
3
00
0
OFFCNC
2
1
0
ACDIV
00 0
000
0
0
Figure 36-9. SSD Prescale and Divider Factor Register (PRESCALE)
The function of the PRESCALE register bits is shown in Table 36-10 below:
Table 36-10. PRESCALE Register Field Description
Field
Description
14-12
BLNDIV - Blanking Counter Clock Divider Select. The frequency for updating the down counter in the
blanking phase of the next BISs is derived from the bus clock according to the formula
<down counter clock> = <bus clock> / (8 * 2^BLNDIV)
According to this formula the divider factors are:
000 8
001 16
010 32
011 64
100 128
101 256
110 512
111 1024
10-8
ITGDIV - Integration Counter Clock Divider Select. The frequency for updating the down counter in the
integration phase of the next BISs is derived from the bus clock according to the formula
<down counter clock> = <bus clock> / (8 * 2^ITGDIV)
According to this formula the divider factors are:
000 8
001 16
010 32
011 64
100 128
101 256
110 512
111 1024
36-10
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor