PXD10RM Datasheet, PDF (775/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

21.6.1.1 Peripheral Interrupt Requests
An interrupt event in a peripheral’s hardware sets a flag bit that resides in the peripheral. The interrupt
request from the peripheral is driven by that flag bit.
The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time
that the INTC starts to drive the interrupt request to the processor is three clocks.
External interrupts are handled by the SIU (see Section 37.6.4, External interrupts”).
21.6.1.2 Software configurable Interrupt Requests
An interrupt request is triggered by software by writing a 1 to a SETx bit in
INTC_SSCIR0_3–INTC_SSCIR4_7. This write sets the corresponding flag bit, CLRx, resulting in the
interrupt request. The interrupt request is cleared by writing a 1 to the CLRx bit.
The time from the write to the SETx bit to the time that the INTC starts to drive the interrupt request to the
processor is four clocks.
21.6.1.3 Unique Vector for Each Interrupt Request Source
Each peripheral and software configurable interrupt request is assigned a hardwired unique 9-bit vector.
Software configurable interrupts 0–7 are assigned vectors 0–7 respectively. The peripheral interrupt
requests are assigned vectors 8 to as high as needed to include all the peripheral interrupt requests. The
peripheral interrupt request input ports at the boundary of the INTC block are assigned specific hardwired
vectors within the INTC (see Table 21-1).
21.6.2 Priority management
The asserted interrupt requests are compared to each other based on their PRIx values set in
INTC_PSR0_3–INTC_PSR204_206. The result is compared to PRI in the associated INTC_CPR. The
results of those comparisons manage the priority of the ISR executed by the associated processor. The
associated LIFO also assists in managing that priority.
21.6.2.1 Current Priority and Preemption
The priority arbitrator, selector, encoder, and comparator subblocks shown in Figure 21-1 compare the
priority of the asserted interrupt requests to the current priority. If the priority of any asserted peripheral or
software configurable interrupt request is higher than the current priority for a given processor, then the
interrupt request to the processor is asserted. Also, a unique vector for the preempting peripheral or
software settable interrupt request is generated for INTC interrupt acknowledge register (INTC_IACKR),
and if in hardware vector mode, for the interrupt vector provided to the processor.
21.6.2.1.1 Priority Arbitrator Subblock
The priority arbitrator subblock for each processor compares all the priorities of all of the asserted interrupt
requests assigned to that processor, both peripheral and software configurable. The output of the priority
arbitrator subblock is the highest of those priorities assigned to a given processor. Also, any interrupt
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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