PXD10RM Datasheet, PDF (950/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

25.4.3.14 Processor Low-Power Mode Exit
If the mode transition is from any of the low-power modes HALT, STOP, or STANDBY to RUN0…3, the
MC_ME requests the processor to exit from its halted or stopped state. This step is executed only after the
Processor and Memory Clock Enable process is completed.
25.4.3.15 System Clock Switching
Based on the SYSCLK bit field of the ME_<current mode>_MC and ME_<target mode>_MC registers,
if the target and current system clock configurations differ, the following method is implemented for clock
switching.
• The target clock configuration for the 16MHz int. RC osc. is effective only when the S_FIRC bit
of the ME_GS register is set by hardware (i.e. the fast internal RC oscillator (16MHz) has
stabilized).
• The target clock configuration for the div. 16MHz int. RC osc. is effective only when the S_FIRC
bit of the ME_GS register is set by hardware (i.e. the fast internal RC oscillator (16MHz) has
stabilized).
• The target clock configuration for the div. 4-16MHz ext. osc. is effective only when the S_FXOSC
bit of the ME_GS register is set by hardware (i.e the fast external crystal oscillator (4-16MHz) has
stabilized).
• The target clock configuration for the primary freq. mod. PLL is effective only when the
S_FMPLL0 bit of the ME_GS register is set by hardware (i.e. the primary frequency modulated
phase locked loop has stabilized).
• If the clock is to be disabled, the SYSCLK bit field should be programmed with “1111”. This is
possible only in the STOP and TEST modes. In the STANDBY mode, the clock configuration is
fixed, and the system clock is automatically forced to ‘0’.
The current system clock configuration can be observed by reading the S_SYSCLK bit field of the ME_GS
register, which is updated after every system clock switching. Until the target clock is available, the system
uses the previous clock configuration.
System clock switching starts only after
• the Clock Sources Switch-On process has completed if the target system clock source needs to be
switched on
• the FMPLL0 Switch-On process has completed if the target system clock is the primary freq. mod.
PLL
• the Peripheral Clocks Disable process is completed in order not to change the system clock
frequency before peripherals close their internal activities
An overview of system clock source selection possibilities for each mode is shown in Table 25-17. A ‘’
indicates that a given clock source is selectable for a given mode.
25-44
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor