PXD10RM Datasheet, PDF (293/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

.
Address:
Base + 0x000C (DSPIx_CTAR0)
Base + 0x0010 (DSPIx_CTAR1)
Base + 0x0014 (DSPIx_CTAR2)
Base + 0x0018 (DSPIx_CTAR3)
Base + 0x001C (DSPIx_CTAR4)
Base + 0x0020 (DSPIx_CTAR5)
Base + 0x0024 (DSPIx_CTAR6)
Base + 0x0028 (DSPIx_CTAR7)
0
1
R
DBR
W
Reset 0 1
2
3
FMSZ
11
4
5
6
7
8
9
CPO CPH LSB
L A FE
PCSSCK
100000
10
11
PASC
00
Access: R/W
12
13
14
15
PDT
PBR
0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
CSSCK
ASC
DT
BR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-5. DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn)
Table 11-5. DSPIx_CTARn Field Descriptions
Field
Descriptions
0
DBR
Double Baud Rate. The DBR bit doubles the effective baud rate of the Serial Communications Clock
(SCK). This field is only used in Master Mode. It effectively halves the Baud Rate division ratio
supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK).
When the DBR bit is set, the duty cycle of the Serial Communications Clock (SCK) depends on the
value in the Baud Rate Prescaler and the Clock Phase bit as listed in Table 11-6. See the BR field
description for details on how to compute the baud rate. If the overall baud rate is divide by two or
divide by three of the system clock then neither the Continuous SCK Enable or the Modified Timing
Format Enable bits should be set.
0 The baud rate is computed normally with a 50/50 duty cycle
1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler
1–4
FMSZ[0:3]
Frame Size. The FMSZ field selects the number of bits transferred per frame. The FMSZ field is used
in Master Mode and Slave Mode. Table 11-7 lists the frame size encodings.
When operating in TSB confirmation, the FMSZ defines the point with in the 32-bit (maximum length)
frame where control of the CS switches from the DSPI_DSICR to the DSPI_DSICR1 register. The
cross over point must range between 4 bits and 16 bits and is encoded per Table 11-7. The remaining
frame after the cross over point, regardless of how many bits are remaining, will be controlled by the
DSPI_DSICR1 register.
5
CPOL
Clock Polarity. The CPOL bit selects the inactive state of the Serial Communications Clock (SCK).
This bit is used in both Master and Slave Mode. For successful communication between serial
devices, the devices must have identical clock polarities. When the continuous selection format (see
Section 11.8.5.5, Continuous Selection Format”) is selected, switching between clock polarities
without stopping the DSPI can cause errors in the transfer due to the peripheral device interpreting
the switch of clock polarity as a valid clock edge.
0 The inactive state value of SCK is low
1 The inactive state value of SCK is high
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-11