PXD10RM Datasheet, PDF (235/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

9.4 Memory map and register description
9.4.1 Memory map
The overall address map organization is shown in Table 9-7.
Whenever an access to either an absent register or absent channel is performed the eMIOS200 responds
asserting Transfer Error signal from the slave bus interface, as well as for access to reserved address.
Table 9-7. eMIOS200 memory map
eMIOS200[n] Base Address
0x000
0x003
0x004
0x007
0x008
0x00B
0x00C
0x00F
0x010
0x11F
0x120
0x21F
0x220
0x31F
0x320
0xFFF
Description
Module Configuration register (EMIOSMCR)
Global FLAG register (EMIOSGFLAG)
Output Update Disable (EMIOSOUDIS)
Disable Channel (EMIOSUCDIS)
reserved
Channel [8]
to
Channel [15]
Channel [16]
to
Channel [23]
reserved
Location
on page 10
on page 12
on page 13
on page 14
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—
9.4.1.1 Unified Channel Memory Map
Addresses of Unified Channel registers are specified as offsets from the channel’s base address, otherwise
the eMIOS200 base address is used as reference.
Table 9-8 describes the Unified Channel memory map.
Table 9-8. Unified Channel Memory Map
UC[n] Base Address
Description
0x00
A register (EMIOSA[n])
0x04
B register (EMIOSB[n])
0x08
Counter register (EMIOSCNT[n])
PXD10 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
9-9
Preliminary—Subject to Change Without Notice