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PXD10RM Datasheet, PDF (117/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller
4.2.5.2 SWT Control Register (SWT_CR)
The SWT_CR contains fields for configuring and controlling the SWT. This register is read only if either
the SWT_CR.HLK or SWT_CR.SLK bits are set.
Offset 0x0000
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10 11 12
13
14 15
R MAP MAP MAP MAP 0
0
0
0
0
0
0
0
0
0
0
0
W0
1
2
3
Reset 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19 20 21
22
23
24
25
26
27 28
29
30
31
R0
0
0
0
0
0
0
RIA WND ITR HLK SLK CSL STP FRZ WEN
W
Reset 0
0
0
0
0
0
0
1
0
0
0
1
1
0
1 See
note
Note: SWT_CR[WEN] value is copied from configuration bit NVUSR0[WATCHDOG_EN] during reset
Figure 4-13. SWT Control Register (SWT_CR)
The SWT_CR reset value is 0x8000_011A or 0x8000_011B, corresponding to MAP0 = 1 (only CPU
access allowed), RIA = 1 (reset on invalid SWT access), SLK = 1 (soft lock), CSL = 1 (IRC clock source
for counter), FRZ = 1 (freeze available while debugging), WEN = 0 or 1 (copied from configuration bit
NVUSR0[WATCHDOG_EN]).
Table 4-7. SWT_CR field descriptions
Field
Description
MAPn
RIA
WND
ITR
HLK
Master Access Protection for Master n. The platform bus master assignments are device specific.
0 = Access for the master is not enabled
1 = Access for the master is enabled
Reset on Invalid Access.
0 = Invalid access to the SWT generates a bus error
1 = Invalid access to the SWT causes a system reset if WEN=1
Window Mode.
0 = Regular mode, service sequence can be done at any time
1 = Windowed mode, the service sequence is only valid when the down counter is less than the value in
the SWT_WN register.
Interrupt Then Reset.
0 = Generate a reset on a time-out
1 = Generate an interrupt on an initial time-out, reset on a second consecutive time-out
Hard Lock. This bit is only cleared at reset.
0 = SWT_CR, SWT_TO and SWT_WN are read/write registers if SLK=0
1 = SWT_CR, SWT_TO and SWT_WN are read only registers
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
4-13