PXD10RM Datasheet, PDF (1016/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

NOTE
Configuration data depending from the value of the QMODE bit must be
left at their reset values when they are not applicable.
Address: QSPI_BASE + 0x000
0
R
W
1
23
4
5
6
00
MTF
E
Write: QMODE: Disabled Mode
DIS_TXF, DIS_RXF: Enabled Mode
All Other: Anytime
7
8
9
10 11 12
13 14
15
Reset 0
0 00 0 0
0
0 00000000
16
R
W
17 18 19 20
21
22
23
24
25
26
27
28
29
30
31
00
00
SMPL_PT
VMID
Reset 0
1 00 0 0
0
0 00000001
Figure 30-2. Module Configuration Register (QSPI_MCR)
Table 30-9. QSPI_MCR Field Descriptions
Field
Description
MSTR
Master/Slave Mode Select. Only applicable if QMODE is cleared. The MSTR bit configures the
QuadSPI for either SPI Master Mode or SPI Slave Mode.
0 QuadSPI is in SPI Slave Mode
1 QuadSPI is in SPI Master Mode
CONT_SCK
E
Continuous SCK Enable. Only applicable if QMODE is cleared. The CONT_SCKE bit enables the
Serial Communication Clock (SCK) to run continuously. See Section 30.5.2.9, Continuous Serial
Communications Clock,” for details.
0 Continuous SCK disabled
1 Continuous SCK enabled
FRZ
Freeze. Only applicable if QMODE is cleared. The FRZ bit enables the QuadSPI transfers to be
stopped on the next frame boundary when the MCU is stopped by a debugger.
0 Do not halt serial transfers
1 Halt serial transfers
MTFE
Modified Timing Format Enable. Only applicable if QMODE is cleared. The MTFE bit enables a
modified transfer format to be used. See Section 30.5.2.8.4, Modified SPI Transfer Format (MTFE =
1, CPHA = 1),” for more information.
0 Modified SPI transfer format disabled
1 Modified SPI transfer format enabled
30-12
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor