PXD10RM Datasheet, PDF (292/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Address: Base + 0x0008
Access: R/W
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SPI_TCNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-4. DSPI Transfer Count Register (DSPIx_TCR)
Table 11-4 describes the field in the DSPI transfer count register.
Table 11-4. DSPIx_TCR Field Descriptions
Field
Description
0–15 SPI transfer counter. Counts the number of SPI transfers the DSPI makes. The SPI_TCNT field is incremented
SPI_TCNT every time the last bit of an SPI frame is transmitted. A value written to SPI_TCNT presets the counter to that value.
[0:15] SPI_TCNT is reset to zero at the beginning of the frame when the CTCNT field is set in the executing SPI
command. The transfer counter ‘wraps around,’ incrementing the counter past 65535 resets the counter to zero.
16–31 Reserved.
11.7.2.3 DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn)
The DSPI modules each contain eight clock and transfer attribute registers (DSPIx_CTARn) which are
used to define different transfer attribute configurations. Each DSPIx_CTAR controls:
• Frame size
• Baud rate and transfer delay values
• Clock phase
• Clock polarity
• MSB or LSB first
At the initiation of an SPI transfer, control logic selects the DSPIx_CTAR that contains the transfer’s
attributes.Do not write to the DSPIx_CTARs while the DSPI is running.
In master mode, the DSPIx_CTARn registers define combinations of transfer attributes such as frame size,
clock phase and polarity, data bit ordering, baud rate, and various delays. In slave mode, a subset of the bit
fields in the DSPIx_CTAR0 and DSPIx_CTAR1 registers are used to set the slave transfer attributes. Refer
to the individual bit descriptions for details on which bits are used in slave modes.
When the DSPI is configured as an SPI master, the CTAS field in the command portion of the TX FIFO
entry selects which of the DSPIx_CTAR registers is used on a per-frame basis. When the DSPI is
configured as an SPI bus slave, the DSPIx_CTAR0 register is used.
11-10
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor