PXD10RM Datasheet, PDF (498/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 15-19. TCDn 32-bit memory structure (continued)
0x1000 + (32 x n) + 0x1c
Beginning “Major” Iteration Count (biter)
Channel Control/Status
(bwc, major.linkch, done, active,
major.e_link, e_sg, d_req, int_half, int_maj,
start)
Figure 15-19 and Table 15-20 define word 0 of the TCDn structure, the saddr field.
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x00
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
saddr[0:15]
W
RESET: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
saddr[16:31]
W
RESET: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= Unimplemented
Figure 15-19. TCDn Word 0 (TCDn.saddr) Field
Name
saddr[[0:31]
Table 15-20. TCDn Word 0 (TCDn.saddr) field description
Description
Source address
Value
Memory address pointing to the source data.
Figure 15-20 and Table 15-21 define word 1 of the TCDn structure, the soff and transfer attribute fields.
0
R
W
RESET: -
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x04
1 2 3 4 5 6 7 8 9 10 11 12
smod[0:4]
ssize[0:2]
dmod[0:4]
13 14 15
dsize[0:2]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
soff[16:31]
W
RESET: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= Unimplemented
Figure 15-20. TCDn Word 1 (TCDn.{soff,smod,ssize,dmod,dsize}) Fields
15-28
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor