PXD10RM Datasheet, PDF (1071/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 30-49. Oak Family QuadSPI Compatibility with the QuadSPI
Oak Family Control Bits
QuadSPI Corresponding Control Bits
Corresponding QSPI_CTAR Register Setting
BITS
E
CTAS[0
]
DT
CTAS[1
]
DSCK
CTAS[2
]
QSPI_CTAR
x
FMSZ
PDT
0
0
0
0
1111 10
0
0
1
1
1111 10
0
1
0
2
1111 user¹
0
1
1
3
1111 user
1
0
0
4
user 10
1
0
1
5
user 10
1
1
0
6
user user
1
1
1
7
user user
1 _{Selected by user}
DT
PCSSC
K
CSSCK
0011
00
0011 user
user
00
user user
0011
00
0011 user
user
00
user user
0000
user
0000
user
0000
user
0000
user
30.6.5 Calculation of FIFO Pointer Addresses - SPI Modes Only
The user has complete visibility of the TX and RX FIFO contents through the FIFO registers, and valid
entries can be identified through a memory mapped pointer and a memory mapped counter for each FIFO.
The pointer to the first-in entry in each FIFO is memory mapped. For the TX FIFO the first-in pointer is
the Transmit Next Pointer (TXNXTPTR). For the RX FIFO the first-in pointer is the Pop Next Pointer
(POPNXTPTR). Figure 30-36 illustrates the concept of first-in and last-in FIFO entries along with the
FIFO Counter. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO.
See Section 30.5.2.5, Transmit First In First Out (TX FIFO) Buffering Mechanism,” and Section 30.5.2.6,
Receive First In First Out (RX FIFO) Buffering Mechanism,” for details on the FIFO operation.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-67